1. Field of the Invention
The invention relates to synchronous digital circuits. More particularly, the invention relates to a method and apparatus for achieving deterministic behavior in a first synchronous system which is clocked by a first clock generator where the first system responds to input signals from a second system which is not clocked by the first clock generator.
2. Cross Reference to Related Copending Applications
The present application is related to copending U.S. Pat. application Ser. No. 07/670,289 entitled "SCANNABLE SYSTEM WITH ADDRESSABLE SCAN RESET GROUPS", by Robert Edwards et al, which was filed Mar. 15, 1991 Said copending application is assigned to the assignee of the present application and its disclosure is incorporated herein by reference.
3. Cross Reference to Related Patents
U.S. Patents are assigned to the assignee of the present application and are further incorporated herein by reference: (A) U.S. Pat. No. 4,244,019, DATA PROCESSING SYSTEM INCLUDING A PROGRAM-EXECUTING SECONDARY SYSTEM CONTROLLING A PROGRAM-EXECUTING PRIMARY SYSTEM, issued to Anderson et al, Jan. 6, 1981; (B) U.S. Pat. No. 4,752,907, INTEGRATED CIRCUIT SCANNING APPARATUS HAVING SCANNING DATA LINES FOR CONNECTING SELECTED DATA LOCATIONS TO AN I/0 TERMINAL, issued to Si, et al. Jun. 21, 1988; (C) U.S. Pat. No. 4,819,166, MULTI-MODE SCAN APPARATUS, issued to Si et al Apr. 4, 1989; (D) U.S. Pat. No. 4,661,953, ERROR TRACKING APPARATUS IN A DATA PROCESSING SYSTEM, issued to Venkatesh et al, Apr. 28, 1987; (E) U.S. Pat. No. 4,835,728 DETERMINISTIC CLOCK CONTROL APPARATUS FOR A DATA PROCESSING SYSTEM, issued to Si, et al., May 30, 1989; and (F) U.S. Pat. No. 4,855,616, APPARATUS FOR SYNCHRONOUSLY SWITCHING FREQUENCY SOURCE, issued to Wang et al., Aug. 8, 1989.
4. Description of the Related Art
A deterministic system is one whose behavior may be exactly replicated one run after the next. Deterministic behavior is desireable in computer systems or other sequential state machines, especially during the debugging of software and/or hardware driven processes.
Each deterministic "run" of a sequential state machine takes that machine from a known initial state to a target state (e.g., the state in which an error condition is first recognized) by following substantially the same sequence of intermediate states as taken by other (previous or future) deterministic runs.
When a system is being debugged, the same software and/or hardware driven process is repeatedly executed while a system monitoring means collects information from a different parts of the system. In each execution, the monitoring means scans through the system looking for logic faults. When a fault is detected, the monitoring means tries to trace backwards both temporally and geographically from the point of detection to a point of origin to thereby discover when, where and how the fault first arose. If the system under test does not exhibit deterministic behavior, it would be difficult if not impossible to isolate the origin of system errors in this manner.
In many circumstances, the system which is to be tested (also referred to hereafter as the "main system") has to respond to input signals supplied from a nonsynchronously running second system.
The response of the main system to such input signals may define a substantial change in the behavior of the main system.
Maintaining deterministic behavior in the main system under such circumstances is difficult because a basic premise of determinism might be violated. The premise is that exactly the same inputs are delivered to the main system at exactly the same clock cycles, one run after the next. When a nonsynchronously running second system supplies behavior changing input signals to the main system, those signals can arrive at arbitrary times relative to the clock cycles of the main system and the behavior of the main system will not be exactly the same in every run.